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general description the max5215/max5217 are pin-compatible 14-bit and 16-bit digital-to-analog converters (dacs). the max5215/max5217 are single-channel, low-powered, buffered voltage-output dacs. the devices use a preci- sion external reference applied through the high resis - tance input for rail-to-rail operation and low system power consumption. the max5215/max5217 accept a wide 2.7v to 5.5v supply voltage range. power consumption is extremely low to accommodate most low-power and low-voltage applications. the max5215/max5217 have an i 2 c-compatible, 2-wire serial interface that operates at clock rates up to 400khz. on power-up, the max5215/max5217 reset the dac out- put to zero, providing additional safety for applications that drive valves or other transducers that need to be off on power-up. the dac output is buffered resulting in a low supply current of 80a (max) and a low offset error of 0.25mv. an asynchronous active-low input, aux, is provided. this input can be programmed to support clear or load dac operations, independent of the serial interface. the max5215/max5217 are available in an ultra-small (3mm x 5mm), 8-pin maxm package and are specified over the -40c to +105c extended industrial temperature range. applications features s low-power consumption (80a, max) s 18s settling time s 16-/14-bit resolution in a 3mm x 5mm, 8-pin max package s relative accuracy ? 0.4 lsb inl (max5215, 14 bit) typ, 1 lsb (max) ? 1.2 lsb inl (max5217, 16 bit) typ, 4 lsb (max) s guaranteed monotonic over all operating range s low gain and offset error s wide 2.7v to 5.5v supply range s rail-to-rail buffered output operation s safe power-up-reset to zero dac output s i 2 c-compatible 400khz serial interface s user-programmable aux input functions ? clr, clear to 0, midscale, or full scale ? ldac, asynchronous load dac s 256ki reference input resistance for low-power operation s buffered voltage output directly drives 10ki loads s output power-down terminated with 1ki or 100ki to ground or left high impedance functional block diagram ordering information appears at end of data sheet. max is a registered trademark of maxim integrated products, inc. remote sensing portable instrumentation communication systems automatic tuning gain and offset adjustment power amplifier control automatic test equipment process control and servo loops data acquisition programmable voltage and current sources 19-6469; rev 0; 11/12 for related parts and recommended products to use with this part, refer to: www.maximintegrated.com/max5215.related code register i 2 c serial interface dac register aux = clr/ ldac por 14 -/16-bit dac buffer 100ki 1ki addr scl sda gnd out v dd ref ( ) for aux configured as clr max5215 max5217 max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maximintegrated.com.
2 v dd to gnd ............................................................. -0.3v to +6v addr, ref, out, aux to gnd ....... -0.3v to the lower of (v dd + 0.3v) and +6v scl, sda, to gnd .................................................. -0.3v to +6v continuous power dissipation (t a = +70nc) fmax (derate at 4.8mw/nc above 70nc) .................... 387mw maximum current into any input or output .................... q50ma operating temperature range ........................ -40nc to +105nc storage temperature range ............................ -65nc to +150nc lead temperature (soldering, 10s) ................................ +300nc soldering temperature (reflow) ...................................... +260nc fmax junction-to-ambient thermal resistance (b ja ) ........ 206n c/w junction-to-case thermal resistance (b jc ) ............... 42n c/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera- tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics (v dd = 2.7v to 5.5v, v ref = 2.5v to v dd , c l = 60pf, r l = 10ki, t a = -40nc to 105nc, unless otherwise noted. typical values are at t a = +25nc.)(note 2) package thermal characteristics (note 1) parameter symbol conditions min typ max units static accuracy (note 3) resolution n max5215 14 bits max5217/max5217b 16 integral nonlinearity inl max5215 (14 bit) (note 4) -1 q0.4 +1 lsb max5217 (16 bit) (note 4) -4 q1.2 +4 max5217b (16 bit) (note 4) -8 q 3 +8 differential nonlinearity dnl max5215 (14 bit) (note 4) -1 q0.1 +1 lsb max5217/5217b (16 bit) (note 4) -1 q0.25 +1 offset error oe max5215/5217 (note 5) -1.25 q0.25 +1.25 mv max5217b (note 5) -3 q0.5 -3 offset-error drift q1.6 fv/nc gain error ge max5215/5217 (note 5) -0.06 -0.04 0 %fs max5217b (note 5) -0.10 -0.04 0 gain temperature coefficient q2 ppm fs/ nc reference input reference-input voltage range v ref 2 v dd v reference-input impedance r ref 200 256 ki dac output output voltage range (note 6) no load 0 v dd v 10ki load to gnd 0 v dd - 0.2 10ki load to v dd 0.2 v dd dc output impedance 0.1 i maxim integrated max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface
3 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ref = 2.5v to v dd , c l = 60pf, r l = 10ki, t a = -40nc to 105nc, unless otherwise noted. typical values are at t a = +25nc.)(note 2) parameter symbol conditions min typ max units maximum capacitive load (no sustained oscillations) c l series resistance = 0i 0.1 nf series resistance = 1ki 15 ff resistive load (note 7) r l 5 ki short-circuit current v dd = 5.5v -25 q6 +25 ma power-up time from power-down mode 25 fs dynamic performance (note 7) voltage-output slew rate sr positive and negative 0.5 v/fs voltage-output settling time ? scale to ? scale, to q0.5 lsb, 14 bit. 18 fs reference C3db bandwidth bw hex code = 2000 (max5215), hex code = 8000 (max5217) 100 khz digital feedthrough code = 0, all digital inputs from 0v to v dd , scl < 400khz 1.0 nvs dac glitch impulse major code transition 5 nvs output noise 1khz 73 nv/hz 10khz 70 integrated output noise 0.1hz to 10hz 3.5 fv p-p power requirements supply voltage v dd 2.7 5.5 v supply current i dd no load; all digital inputs at 0v or v dd , supply current only; excludes reference input current. 70 80 fa power-down supply current pdi dd no load, all digital inputs at 0v or v dd 0.4 2 fa digital inputs (scl, sda, aux, addr ) input high voltage v ih 0.7 x v dd v input low voltage v il 0.3 x v dd v hysteresis voltage v hys 0.15 v input leakage current i in v in = 0v or v dd q0.1 q1 fa input capacitance (note 7) c in 10 pf addr pullup/pulldown strength (note 8) 30 50 90 ki digital output (sda) output low voltage v ol i sink = 3ma 0.2 v maxim integrated max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface
4 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ref = 2.5v to v dd , c l = 60pf, r l = 10ki, t a = -40nc to 105nc, unless otherwise noted. typical values are at t a = +25nc.)(note 2) note 2: electrical specifications are production tested at t a = +25c and t a = +105c. specifications over the entire operating temperature range are guaranteed by design and characterization. typical specifications are at t a = +25c and are not guaranteed. note 3: static accuracy tested without load. note 4: linearity is tested within 20mv of gnd and v dd . note 5: gain and offset is tested within 20mv of gnd and v dd . note 6: subject to offset and gain error limits and v ref settings. note 7: specification is guaranteed by design and characterization. note 8: unconnected conditions on the addr_ inputs are sensed through a resistive pullup and pulldown operation; for proper operation, the addr_ inputs must be connected to v dd , gnd, or left unconnected with minimal capacitance. parameter symbol conditions min typ max units timing characteristics scl clock frequency f scl 400 khz sbus free time between a stop and a start condition t buf 1.3 fs hold time for a repeated start condition t hd;sta 0.6 fs scl pulse width low t low 1.3 fs scl pulse width high t high 0.6 fs setup time for repeated start condition t su;sta 0.6 fs data hold time t hd;dat 0 900 ns data setup time t su;dat 100 ns sda and scl receiving rise time t r 20 + c b /10 300 ns sda and scl receiving fall time t f 20 + c b /10 300 ns sda transmitting fall time t f 20 + c b /10 250 ns setup time for stop condition t su;sto 0.6 fs bus capacitance allowed c b v dd = 2.7v to 5.5v 10 400 pf pulse width of suppressed spike t sp 50 ns clr removal time prior to a recognized start t clrsta 100 ns clr pulse width low t clpw 20 ns ldac pulse width low t ldpw 20 ns sclk rise to ldac fall hold t ldh applies to execution edge 400 ns maxim integrated max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface
5 typical operating characteristics (v dd = 5v, t a = +25c, unless otherwise noted.) figure 1. i 2 c serial interface timing diagram t su;sto t r t sp t hd;sta t su;sta t f t high t hd;dat t low t clpw t clrsta t ld h t ldpw t hd;sta t f s s s r p sd a sc l cl r ld ac t su;dat t r t buf integral nonlinearity vs. digital input code max5215 toc01a digital input code (lsb) inl (lsb) 12288 8192 4096 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 16384 max5215 v ref = 5v integral nonlinearity vs. digital input code max5215 toc01b digital input code (lsb) inl (lsb) 12288 8192 4096 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 16384 max5215 v ref = 2.5v integral nonlinearity vs. digital input code max5215 toc02a digital input code (lsb) inl (lsb) 49152 32768 16384 -2 -1 0 1 2 3 -3 0 65536 max5217 v ref = 5v maxim integrated max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface
6 typical operating characteristics (continued) (v dd = 5v, t a = +25c, unless otherwise noted.) integral nonlinearity vs. digital input code max5215 toc02b digital input code (lsb) inl (lsb) 49152 32768 16384 -2 -1 0 1 2 3 -3 0 65536 max5217 v ref = 2.5v integral nonlinearity vs. supply voltage max5215 toc04b supply voltage (v) inl (lsb) 5.1 4.7 4.3 3.9 3.5 3.1 -2 -1 0 1 2 3 -3 2.7 5.5 max min max5217 inl min/max (v ref = 5.0v/2.5v) max5215 toc03 device number inl min/max (lsb) 19 17 13 15 3579 11 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 -3.0 1 v ref = 5.0v v ref = 2.5v v ref = 5.0v v ref = 2.5v max5217 integral nonlinearity vs. temperature max5215 toc05a temperature (c) inl (lsb) 80 60 -20 0 20 40 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 -40 100 max5215 max min integral nonlinearity vs. supply voltage max5215 toc04a supply voltage (v) inl (lsb) 5.1 4.7 3.1 3.5 3.9 4.3 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 2.7 5.5 max5215 max min integral nonlinearity vs. temperature max5215 toc05b temperature (c) inl (lsb) 80 60 40 20 0 -20 -2 -1 0 1 2 3 -3 -40 100 max min max5217 max(abs(inl)) distribution vs. temperature max5215 toc06a lsb count (units) 0.60 0.10 0.30 0.40 0.50 0.20 10 20 30 40 50 60 70 80 0 0 0.70 max5215 -40c +25c +105c max(abs(inl)) distribution vs. temperature max5215 toc06b lsb count (units) 2.4 0.4 1.2 1.6 2.0 0.8 10 20 30 40 50 60 70 80 0 0 2.8 max5217 -40c +25c +105c maxim integrated max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface
7 maxim integrated max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface typical operating characteristics (continued) (v dd = 5v, t a = +25c, unless otherwise noted.) differential nonlinearity vs. digital input code max5215 toc07a digital input code (lsb) dnl (lsb) 12288 8192 4096 -0.3 -0.1 0.1 0.3 0.5 -0.5 0 16384 max5215 v ref = 5v differential nonlinearity vs. digital input code max5215 toc07d digital input code (lsb) dnl (lsb) 49152 32768 16384 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 65536 max5217 v ref = 2.5v differential nonlinearity vs. supply voltage max5215 toc09b supply voltage (v) dnl (lsb) 5.1 4.7 3.9 4.3 3.5 3.1 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 2.7 5.5 max5217 max min differential nonlinearity vs. digital input code max5215 toc07b digital input code (lsb) dnl (lsb) 12288 8192 4096 -0.3 -0.1 0.1 0.3 0.5 -0.5 0 16384 max5215 v ref = 2.5v dnl min/max (v ref = 5.0v/2.5v) max5215 toc08 device number dnl (lsb) 19 17 13 15 5 7 9 11 3 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 1 v ref = 5.0v v ref = 2.5v v ref = 5.0v v ref = 2.5v max5217 differential nonlinearity vs. digital input code max5215 toc07c digital input code (lsb) dnl (lsb) 49152 32768 16384 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 65536 max5217 v ref = 5v differential nonlinearity vs. supply voltage max5215 toc09a supply voltage (v) dnl (lsb) 5.1 4.7 3.9 4.3 3.5 3.1 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 2.7 5.5 max5215 max min differential nonlinearity vs. temperature max5215 toc10a temperature (c) max min dnl (lsb) 100 80 40 60 0 20 -20 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 -40 max5215 differential nonlinearity vs. temperature max5215 toc10b temperature (c) max min dnl (lsb) 100 80 40 60 0 20 -20 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 -40 max5217
8 maxim integrated max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface typical operating characteristics (continued) (v dd = 5v, t a = +25c, unless otherwise noted.) full-scale output vs. temperature max5215 toc18 output voltage (v) 2.492 2.494 2.496 2.498 2.500 2.490 temperature (c) 100 80 60 40 20 0 -20 -40 v ref = 2.5v max5217 max5215 offset error drift vs. temperature distribution max5215 toc13 drift (v/c) count (units) 2.8 3.2 2.4 2.0 1.6 1.2 0.8 0.4 2 4 6 8 10 12 14 0 0 -40c to +105c box method gain error drift vs. temperature distribution max5215 toc16 drift (ppmfs/c) count (units) 0.50 0.40 0.30 0.20 0.10 2 4 6 8 10 12 14 0 0 -40c to +105c box method offset error vs. supply voltage max5215 toc11 supply voltage (v) offset error (mv) 5.1 4.7 4.3 3.9 3.5 3.1 0.2 0.4 0.6 0.8 1.0 0 2.7 5.5 v ref = 2.5v max5217 max5215 supply current vs. temperature max5215 toc19a temperature (c) supply current (a) 80 60 20 40 0 -20 62 64 66 68 70 72 74 76 78 80 60 -40 100 max5215/max5217 no load v dd = v ref v out = midscale v dd = 4v v dd = 2.7v v dd = 5.25v v dd = 5v gain error vs. supply max5215 toc14 supply voltage (v) gain error (%fs) 5.1 4.7 4.3 3.9 3.5 3.1 -0.05 -0.04 -0.03 -0.02 -0.01 0 -0.06 2.7 5.5 v ref = 2.5v max5217 max5215 full-scale output vs. supply voltage max5215 toc17 supply voltage (v) output voltage (v) 5.1 4.7 4.3 3.9 3.5 3.1 2.492 2.494 2.496 2.498 2.500 2.490 2.7 5.5 max5217 max5215 v ref = 2.5v offset error vs. temperature max5215 toc12 temperature (c) offset error (mv) 100 80 60 40 20 0 -20 0.25 0.50 0.75 1.00 1.25 0 -40 max5217 max5215 gain error vs. temperature max5215 toc15 gain error (%fs) -0.05 -0.04 -0.03 -0.02 -0.01 0 -0.06 temperature (c) 100 80 60 40 20 0 -20 -40 max5217 max5215 v ref = 2.5v
9 max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface typical operating characteristics (continued) (v dd = 5v, t a = +25c, unless otherwise noted.) supply current vs. supply voltage max5215 toc20a supply voltage (v) supply current (a) 5.1 4.7 3.9 4.3 3.5 3.1 62 64 66 68 70 72 74 76 78 80 60 2.7 5.5 no load v dd = v ref v out = midscale max5215 max5217 supply current vs. dac code max5215 toc22a code supply current (a) 15,000 12,500 10,000 7500 5000 2500 50 55 60 65 70 75 80 45 0 v ref = 5.0v v ref = 2.5v max5215 no load v dd = v ref supply current vs. supply voltage max5215 toc20b supply voltage (v) supply current (a) 45 50 55 60 65 70 75 80 40 5.1 4.7 3.1 3.5 3.9 4.3 2.7 5.5 no load v dd = v ref v out = zero scale max5217 max5215 max5215 toc19b supply current (a) 45 50 55 60 65 70 75 80 40 supply current vs. temperature temperature (c) 80 60 20 40 0 -20 -40 100 v dd = 4v max5215/max5217 no load v dd = v ref v out = zeroscale v dd = 5v v dd = 5.25v v dd = 2.7v supply current vs. supply voltage (power-down mode) max5215 toc21 supply voltage (v) supply current (a) 5.1 4.7 4.3 3.9 3.5 3.1 0.1 0.2 0.3 0.4 0.5 0.6 0 2.7 5.5 -40c 0c +25c +85c +105c supply current vs. dac code max5215 toc22b code supply current (a) 60,000 50,000 40,000 30,000 20,000 10,000 50 55 60 65 70 75 80 45 0 v ref = 5.0v v ref = 2.5v no load v dd = v ref max5217 v out vs. time (exiting power-down mode) max5215 toc23 out = midscale 1v/div 0v 10s / div max5215/max5217 r l = 10ki v ref = 5v major code transition (0x7fff to 0x8000) max5215 toc24a out = midscale ac-coupled 1mv/div 4s /div max5217 v ref = 5v no load maxim integrated
10 typical operating characteristics (continued) (v dd = 5v, t a = +25c, unless otherwise noted.) settling to 0.5 lsb 14 bit (v dd = v ref = 5v, c l = 100pf) max5215 toc25b 4s /div 17s max5215 /m ax5217 3/4 scale to 1/4 scale major code transition (0x8000 to 0x7fff) max5215 toc24b out = midscale ac-coupled 1mv/div 4s/div max5217 v ref = 5v no load major code transition (0x2000 to 0x1fff) max5215 toc24d out = midscale ac-coupled 1mv/div 4s/div max5215 v ref = 5v no load digital feedthrough max5215 toc26 v out ac-coupled 50mv/div scl 5v/div 400ns/ div major code transition (0x1fff to 0x2000) max5215 toc24c out = midscale ac-coupled 1mv/div 4s/div max5215 v ref = 5v no load settling to 0.5 lsb 14 bit (v dd = v ref = 5v, c l = 100pf) max5215 toc25a 4s /div max5215/m ax5217 1/4 scale to 3/4 scale 18s maxim integrated max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface
11 typical operating characteristics (continued) (v dd = 5v, t a = +25c, unless otherwise noted.) output voltage vs. output current max5215 toc27 output current (ma) output voltage (v) 5 4 3 2 1 2.30 2.35 2.40 2.45 2.50 2.55 2.25 06 v dd = 5v v ref = 5v reference input bandwidth vs. frequency max5215 toc29 input frequency (khz) attenuation (db) 100 10 -15 -10 -5 0 5 -20 1 1000 supply current vs. digital input voltage max5215 toc28 digital input voltage (v) digital supply current (a) 500 1000 1500 2000 2500 3000 3500 0 0 12345 v dd = 2.7v high t0 low v ddi = 2.7v low t0 high v dd = 5v low t0 high v dd = 5v high t0 low integrated output noise (0.1hz to 10hz) max5215 toc30 out 1v/div 1s/div frequency (hz) 1k 100k noise (nv rms / hz) 10k 100 10 dac ouput noise density vs. frequency max5215 toc31 75 100 125 150 175 200 50 max5215/ max5217 full-scale (code 0 x ff00) zero-scale (code 0x00ff) midscale (code 0x8000) maxim integrated max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface
12 pin description pin configuration detailed description the max5215/max5217 are 14-bit and 16-bit single- channel, low-power, high reference input resistance, buffered voltage-output dacs. these devices feature a fast 400khz i 2 c serial interface. the max5215/max5217 include a serial-in/parallel-out shift register, internal code and dac registers, a power-on-reset (por) circuit to initialize the dac output to code zero, and an output buffer to allow rail-to-rail operation. the 2.7v to 5.5v wide supply voltage range and low-power consumption accommodate most low-power and low-voltage applica - tions. on power-up, the max5215/max5217 reset the dac output to zero, providing additional safety for appli- cations that drive valves or other transducers that need to be off during power-up. the max5215/max5217 feature a configurable asyn - chronous active-low input ( aux ) that can be programmed by the user to act as either an asynchronous clear input (clr) or a load dac input (ldac). by default, the devic- es operate in clr mode on power-up. dac output (out) the max5215/max5217 include an internal buffer on the dac output. the internal buffer provides improved load regulation and transition glitch suppression for the dac output. the output buffer slews at 0.5v/fs and drives up to 10ki in parallel with 100pf. the analog supply voltage (v dd ) determines the maximum output voltage range of the device as v dd powers the output buffer. under no-load condi tions, the output buffer drives from gnd to v dd , subject to offset and gain errors. with a 10ki load to gnd, the output buffer drives from gnd to within 200mv of v dd . with a 10ki load to v dd , the output buffer drive from v dd to within 200mv of gnd. pin name function 1 ref reference voltage input. bypass ref with a 0.1ff capacitor to gnd. 2 addr i 2 c device address input. pull high, low, or do not connect to set the two lsbs of the device address. 3 scl i 2 c serial clock input 4 sda i 2 c serial data input 5 aux user-configurable active-low asynchronous input. when configured as clr mode: drive aux low to clear the contents of the input code and the dac registers and return the dac to a user-selectable return state (default). when configured as ldac mode: drive aux low to load the pending code register content to the active dac register. 6 out buffered dac voltage output 7 v dd supply voltage. bypass v dd with a 0.1ff capacitor to gnd. 8 gnd ground 1 2 3 4 8 7 6 5 gnd v dd out aux sda scl addr ref max top view + max5215 max5217 maxim integrated max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface
13 the dac ideal output voltage is defined by: v out = v ref x d/2 n where d = code loaded into the dac register, v ref = reference voltage, n = resolution dac reference (ref) the external reference input features a typical input impedance of 256ki (independent of the dac code) and accepts an input voltage from +2v to v dd . connect an external voltage supply between ref and gnd to apply an external reference. visit www.maximintegrated.com / products / references for a list of available voltage- reference devices. internal register structure the user interface is separated from the dac logic to minimize digital feedthrough. within the serial interface is an input shift register, the contents of which can be routed to the control register or dac, as determined by the user command. within the device, there is a code register followed by a dac latch register (see the functional diagram). the contents of the code register hold pending dac output settings which can later be loaded into the dac register. the code register can be updated using both code and code_load user commands. the contents of the dac register hold the current dac output set - tings. the dac register can be updated directly from the serial interface using the code_load commands or can upload the current contents of the code register using load commands or the ldac logic input. the contents of both code and dac registers are maintained during power-down states, so that when the dac is powered on, the previously stored output setting is restored. any code or load commands issued dur- ing power-down states continue to update the register contents. aux configured as clear input, clr when configured in clr mode, the aux input performs an asynchronous level sensitive clear operation. if clr is pulled low, the code and dac data registers are reset to their clear values as defined by the user configuration settings (see table 9 ). user configuration settings are not affected. if clr is asserted at any point during an i 2 c write sequence, from that point on, and until clr is deas- serted, all i 2 c commands attempting to modify code or dac register contents are ignored. the clr activity is given precedence and the commands are gated. in all cases, the i 2 c interface continues to function according to protocol, however slave ack pulses beyond the com- mand byte acknowledge will not be sent for gated com- mand sequences (notifying the fp that the gated instruc- tions are being ignored). this gating condition remains in effect until the clr condition is removed and a sub- sequent i 2 c start condition is recognized (beginning a new i 2 c write sequence), meeting t clrsta requirements (figure 1). if clr is driven low during an i 2 c command read sequence, the exchange continues as normal, however the data being read back may be stale, having since been cleared. the user may determine the state of the clr pin by issuing a part id read command. an equivalent software clear operation is provided through the sw_clear command. aux configured as load dac input, ldac when configured in ldac mode, the aux input per- forms an asynchronous level sensitive load operation when it is pulled low. internally, a dual register system is provided, with pending dac output settings stored in a code register, while the current output settings are stored in the dac latches. when ldac is pulled low, the dac latches are held in a transparent state, and the code register contents are loaded and stored. this allows several dacs to be updated simultaneously using a common ldac line, or allows the dac to be quickly updated to a pending setting via a single pin operation. users wishing to load new dac data in direct response to i 2 c activity can enable and connect ldac permanent- ly low. users wishing to control the dac update instance independently of the i 2 c instruction should hold ldac high during programming cycles. once the programming is complete, ldac may be strobed and the new dac codes will be loaded (this method allows simultaneous updates of several devices). be sure to observe the t ldh timing requirements (figure 1). a software load operation is provided through the load or code_load command. with the software load opera- tion, the content of the code register will be latched into the dac register regardless of the status and configura- tion of the ldac pin. multiple max5215/max5217 can be loaded synchronously using software load commands in conjunction with the broadcast id. maxim integrated max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface
14 smbus is a trademark of intel corp. table 1. two lsbs of the slave address determined by the addr input i 2 c serial interface the max5215/max5217 feature an i 2 c/smbus k - compatible 2-wire serial interface consisting of a serial data line (sda) and a serial clock line (scl). sda and scl enable communication between the part and the master at clock rates up to 400khz. figure 1 shows the 2-wire interface timing diagram. the master generates scl and initiates data transfer on the bus. the master device writes data to the max5215/max5217 by trans - mitting the proper slave address followed by the register address and then the data word. each transmit sequence is framed by a start (s) or repeated start (sr) condi- tion and a stop (p) condition. each word transmitted to the part is 8 bits long and is followed by an acknowledge clock pulse. a master reading data from the max5215/max5217 must transmit the proper slave address followed by a series of nine scl pulses for each byte of data requested. the max5215/max5217 transmit data on sda in sync with the master-generated scl pulses. the master acknowl- edges receipt of each byte of data. each read sequence is framed by a start or repeated start condition, a not acknowledge, and a stop condition. sda operates as both an input and an open-drain output. a pullup resistor, typically 4.7ki , is required on sda. scl operates only as an input. a pullup resistor, typically 4.7ki , is required on scl if there are multiple masters on the bus, or if the single master has an open-drain scl output. series resistors in line with sda and scl are optional. series resistors protect the digital inputs of the max5215/ max5217 from high voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. the max5215/max5217 can accommodate bus volt - ages higher than v dd up to a limit of 5.5v; bus voltages lower than v dd are not recommended and may result in significantly increased interface currents. i 2 c bit transfer one data bit is transferred during each scl cycle. the data on sda must remain stable during the high period of the scl pulse. changes in sda while scl is high are control signals (see the i 2 c start and stop conditions section). i 2 c start and stop conditions sda and scl idle high when the bus is not in use. a mas- ter initiates communication by issuing a start condition. a start condition is a high-to-low transition on sda with scl high. a stop condition is a low-to-high transition on sda while scl is high (figure 2). a start condition from the master signals the beginning of a transmission to the max5215/max5217. the master terminates trans - mission, and frees the bus, by issuing a stop condition. the bus remains active if a repeated start condition is generated instead of a stop condition. i 2 c early stop and repeated start conditions the max5215/max5217 recognize a stop condition at any point during data transmission except if the stop condition occurs in the same high pulse as a start condition. for proper operation, do not send a stop con- dition during the same scl high pulse as the start con- dition. transmissions ending in an early stop condition will not impact the internal device settings. if the stop occurs during a readback byte, the transmission is termi- nated and a later read mode request will begin transfer of the requested register data from the beginning. figure 2. i 2 c start, repeated start, and stop conditions addr a1 a0 gnd 0 0 n.c. 0 1 v dd 1 1 scl sda ss rp valid start, repeated start, and stop pulses ps p sp p s invalid start /s top pulse pairings -all will be recognized as start s maxim integrated max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface
15 figure 3. i 2 c acknowledge i 2 c slave address the slave address is defined as the seven most signifi- cant bits (msbs) followed by the r/w bit (figure 1). the 5 msbs (a[6:2]) are 00111 with the two lsbs (a[1:0]) deter- mined by the input addr as shown in table 1. setting the r/w bit to 1 configures the max5215/max5217 for read mode. setting the r//w bit to 0 configures the max5215/ max5217 for write mode. the slave address is the first byte of information sent to the max5215/max5217 after the start condition. the max5215/max5217 have the ability to detect an unconnected state on the addr input for additional address flexibility; if leaving the addr input unconnect- ed, be certain to minimize all loading on the pin (i.e. pro - vide a landing for the pin, but do not any board traces. i 2 c broadcast address a broadcast address is provided for the purpose of updating or configuring all max5215/max5217 devices on a given i 2 c bus. all max5215/max5217 acknowledge and respond to the broadcast device address 01010100 regardless of the state of the address input pin. the broadcast is intended for use in write mode only (as indi- cated by r/ w = 0 in the address given) i 2 c acknowledge in write mode, the acknowledge bit (ack) is a clocked 9th bit that the max5215/max5217 use to handshake receipt of each byte of data when in write mode as shown in figure 3 . the max5215/max5217 pull down sda during the entire master-generated 9th clock pulse if the previous byte is successfully received. monitoring ack allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master will retry communication. in read mode, the master pulls down sda during the 9th clock cycle to acknowledge receipt of data when the max5215/max5217 are in read mode. an acknowledge is sent by the master after each read byte to allow data transfer to continue. a not-acknowledge is sent when the master reads the final byte of data from the max5215/ max5217, followed by a stop condition. i 2 c write operation (standard protocol) a master device communicates with the max5215/ max5217 by transmitting the proper slave address followed by command and data words. each transmit sequence is framed by a start or repeated start condition and a stop condition as described above. each word is 8 bits long and is always followed by an acknowledge clock (ack) pulse as shown in figure 4and figure 5. the first byte contains the address of the max5215/max5217 with r/ w = 0 to indicate a write. the second byte contains the register (or command) to be written and the third and fourth bytes contain the data to be written. by repeating register address plus data pairs (byte #2 through byte #4 in figure 4 and figure 5), the user can perform multiple register writes using a single i 2 c command sequence; there is no limit as to how many registers the user can write with a single command. the max5215/max5217 support this capability for all user- accessible write mode commands. i 2 c write operation (multibyte protocol) the max5215/max5217 support a multibyte transfer protocol for some commands. in multibyte mode, once a command is issued, that command is continuously executed based on two byte data blocks for the duration i 2 c operation. essentially, bytes 1 to 4 are processed normally, but for every two bytes of data provided after 1 scl start condition sda 29 clock pulse for acknowledgment acknowledge not acknowledge maxim integrated max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface
16 byte 4, the originally requested command is executed again with the latest byte pair provided as input data (figure 6). multibyte protocol is enforced until a stop condition (or repeated start) is encountered and this provides a higher speed transfer mode that is useful in servo dac applications. i 2 c readback operation each readback sequence is framed by a start or repeated start condition and a stop condition. each word is 8 bits long and is followed by an acknowledge clock pulse (figure 7). the first byte contains the address of the max5215/max5217 with r/ w = 0 to indicate a write. the second byte contains the register that is to be read back. there is a repeated start condition, followed by the device address with r/w = 1 to indicate a read and an acknowledge clock. the final two bytes in the frame contain the register data readback followed by a stop condition. the master has control of the scl line but the max5215/max5217 take over the sda line. following each byte of data read back from the max5215/max5217 the master must acknowledge the transfer by pulling sda low. if additional bytes beyond those required to read back the requested data are provided, the max5215/5217 will continue to read back ones. a user can read back the devices configuration, part id, code register, or dac register contents using the readback programming sequence as shown in figure 7. i 2 c compatibility the max5215/max5217 are fully compatible with exist- ing i 2 c systems. scl and sda are high-impedance inputs; sda has an open drain which pulls the data line low during the 9th clock pulse or as required for data readback. figure 8 shows a typical i 2 c application. figure 5. multiple register write sequence (standard i 2 c protocol) figure 4. i 2 c single register write sequence stop wr ite byte #1: device address start sda scl wr ite byte #2: user comman d wr ite byte #3 : data byte #1 wr ite byte #4 : data byte #2 ack. generated by max5215/ max5217 command executed a 0 011 1a 1a 0r 7r 6r 5r 4r 3r 2r 1r 01 51 41 31 21 11 09 87 65 43 21 0 wa aa a a scl start wr ite ad dress byte #1: i 2 c slave a ddre ss sda commandn executed command1 executed ack. generated by max5215/ max5217 a 00 11 1a 1a 0w aa aa 15 14 13 12 11 10 98 15 14 13 12 11 10 98 aa 76 54 32 10 76 54 32 10 r7 r6 r5 r4 r3 r2 r1 r0 r7 r6 r5 r4 r3 r2 r1 r0 wr ite comm an d1 byte #2: comm an d1 byt e (b[23:16] ) wr ite da ta1 byte #3: da ta1 high byt e (b[15:8] ) wr ite da ta1 byte #4: da ta1 low byt e (b[7:0] ) additional command an d da ta pairs (3 byte blocks ) byte #5: comma ndn byt e (b[23:16] ) byte #6: da tan high byt e (b[15:8]) byte #7: da tan low byt e (b[7:0]) stop maxim integrated max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface
17 figure 7. standard i 2 c read sequence figure 8. typical i 2 c application circuit scl start stop sda ack. generated by max5215 / max5217 a ack. generated by i 2 c master a wr ite ad dress byte #1: i2c sl ave address read address byte #3: i2c sl ave address read data byte #4: da ta1 high byte (b[15:8]) read data byte #5: da ta1 lo w byte (b[7:0]) wr ite comma nd 1 byte #2: comma nd1 byt e repeated start 00 00 1 11 11 1 a1 a0 a1 a0 r7 r6 r5 r4 r3 r2 r1 r0 wr a aa 15 14 13 12 11 10 98 7654 32 10 -a a scl scl sda c +5v sd a addr max5215 max5217 max5215 max5217 scl sd a addr figure 6. multiple register write sequence (multibyte protocol) a scl start wr ite ad dress byte #1: d evi ce ad dress sda re g n up da te d re g n up da te d ack. generated by max5215/ max5217 a 00 11 1a 1a 0w aa a 15 14 13 12 11 10 98 15 14 13 12 11 10 98 aa 76 54 32 10 76 54 32 10 r7 r6 r5 r4 r3 r2 r1 r0 wr ite re gister no . byte #2: fi rs t reg# = n wr ite da ta byte #3: re g(n)[15:8] data wr ite da ta byte #4: re g(n)[7:0] data additional data byte pairs (2 byte blocks ) wr ite da ta byte #x-1: re g(n)[15:8] data wr ite da ta byte #x: re g(n)[7:0] data stop maxim integrated max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface
18 i 2 c user-command register map this section lists the user-accessible commands and registers for the max5215/max5217. table 2 provides detailed information about the command registers. no_op command (0x00) the no_op command (table 3) has no external effect on the device for i 2 c write. the asynchronous clr input has no effect on the no_op command. table 2. i 2 c user write commands table 3. no_op command (0x00) *note: if a user write command is gated by clr, and clr has been asserted during the i 2 c write sequence, the command is ignored and the associated data bytes will not be acknowledged. if a user write command is not gated by clr, the command is executed as normal, regardless of the activity of the clr pin. write command command byte data bytes description clr gated* r7 r6 r5 r4 r3 r2 r1 r0 no-op (0x00) 0 0 0 0 0 0 0 0 dont care no operation: dac settings and modes unaffected n code_load (0x01) 0 0 0 0 0 0 0 1 14-/16-bit code write and load data to the code and dac registers y code (0x02) 0 0 0 0 0 0 1 0 14-/16-bit code write data to the code register y load (0x03) 0 0 0 0 0 0 1 1 dont care load current code register content to the dac register y code_load_m (0x05) 0 0 0 0 0 1 0 1 multiple sets of 14-/16-bit codes similar to code_load command, but accepts multiple sets of dual-byte data following the initial command byte (see the i 2 c write operation (multibyte protocol) section) y code_m (0x06) 0 0 0 0 0 1 1 0 multiple sets of 14-/16-bit codes similar to code command, but accepts multiple sets of dual-byte data following the initial command byte (see the i 2 c write operation (multibyte protocol) section) y user_config (0x08) 0 0 0 0 1 0 0 0 16-bit configuration data user configuration command n sw_reset (0x09) 0 0 0 0 1 0 0 1 dont care software reset n sw_clear (0x0a) 0 0 0 0 1 0 1 0 dont care software clear n reserved any commands not specifically listed above are reserved for maxim internal use only. r7 r6 r5 r4 r3 r2 r1 r0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0000_0000 no_op command dont care dont care command byte data high byte data low byte maxim integrated max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface
19 code_load command (0x01) the code_load command (table 4) is the combina- tion of the code command and load command. the code_load command is executed on the scl rising edge following the 2 nd data byte. upon its execution, the code_load command updates the code register and the dac latch with the user data content provided. the asynchronous clr input gates this command if it is asserted during the i 2 c write sequence. code command (0x02) the code command (table 5) is executed on the scl rising edge following the 2 nd data byte. the code command updates the code register with the user data content provided. the asynchronous clr input gates this command if it is asserted during the i 2 c write sequence. load command (0x03) the load command (table 6) is executed on the scl rising edge following the 2 nd data byte. the load com- mand loads the dac latches with the current contents of the code register. alternatively, a load operation can be achieved by driving the aux input low (when configured as ldac). the asynchronous clr input gates this command if it is asserted during the i 2 c write sequence. code_load_m command (0x05) the code_load_m command (table 7) is the multibyte version of the code_load command. the code_ load_m command is initially executed on the scl rising edge following the 2 nd data byte. the command is subse- quently executed after each pair of data bytes which follow, for the duration of the operation (see the i 2 c write operation (multibyte protocol) section). the asynchronous clr input gates this command if it is asserted during the i 2 c write sequence. table 6. load command table 4. code_load command table 5. code command r7 r6 r5 r4 r3 r2 r1 r0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0000_0011 load command dont care dont care command byte data high byte data low byte r7 r6 r5 r4 r3 r2 r1 r0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0000_0001 16-bit code_load command code and dac registers data code and dac registers data 0000_0001 14-bit code_load command code and dac registers data code and dac registers data dont care command byte data high byte data low byte r7 r6 r5 r4 r3 r2 r1 r0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0000_0010 16-bit code command code register data code register data 0000_0010 14-bit code command code register data code register data dont care command byte data high byte data low byte maxim integrated max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface
20 code_m command (0x06) the code_m command (table 8) is the multibyte ver- sion of the code command. the code_m command is initially executed on the scl rising edge following the 2 nd data byte. the command is subsequently exe - cuted after each pair of data bytes which follow, for the duration of the operation (see the i 2 c write operation (multibyte protocol) section). this command is of practi- cal use when the aux pin is configured as ldac and continuously asserted low. the asynchronous clr input gates this command if it is asserted during the i 2 c write sequence. user_config command (0x08) the user_config command allows the user to select the configuration of the device: setting the clear value to which the dac returns in response to a clear event, configuring the input mode for aux, and setting the power-down mode for the max5215/max5217. the user_config command is executed on the scl rising edge following the 2 nd data byte. table 9 and table 10 describe the command and the configuration bits in detail. the asynchronous clr input has no effect on the user_ config command. table 7. code_load_m command table 8. code_m command table 9. user_config command r7 r6 r5 r4 r3 r2 r1 r0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0000_0101 16-bit code_load_m command code and dac registers data code and dac registers data 0000_0101 14-bit code_load_m command code and dac registers data code and dac registers data dont care command byte data high byte data low byte r7 r6 r5 r4 r3 r2 r1 r0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0000_0110 16-bit code_m command code and dac registers data code and dac registers data 0000_0110 14-bit code_m command code and dac registers data code and dac registers data dont care command byte data high byte data low byte r7 r6 r5 r4 r3 r2 r1 r0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0000_1000 user_config command dont care dont care clear value mode: 00 = default 01 = zero 10 = mid 11 = full aux input mode: 00 = disable 01 = ldac 10 = clr 11 = disable power- down mode: 00 = dac 01 = high-z 10 = 100ki 11 = 1ki data default valueg x x x x x x x x x x 0 0 1 0 0 0 command byte data high byte data low byte maxim integrated max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface
21 sw_reset command (0x09) the sw_reset command (table 11) resets the code register, the dac latch, and all the configurations pro- grammed via the user_config command to the por default values. the sw_reset command is executed on the scl rising edge following the second data byte. the asynchronous clr input has no effect on the sw_reset command. sw_clear command (0x0a) the sw_clear command ( table 12 ) will clear the code register and the dac latch to the clear value selected in the user_config register. the sw_clear command is executed on the scl rising edge following the 2 nd data byte. alternatively, a clear operation can be achieved by driving the aux input low (when configured as clr). the asynchronous clr input has no effect on the sw_clear command. table 10. user_configuration bits (b[5:0]) table 11. sw_reset command table 12. sw_clear command r7 r6 r5 r4 r3 r2 r1 r0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0000_1001 sw_reset command dont care dont care command byte data high byte data low byte r7 r6 r5 r4 r3 r2 r1 r0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0000_1010 sw_clear command dont care dont care command byte data high byte data low byte configuration bits configuration detail clear value (b[5:4]) the dac value to be cleared to in response to a clear event: 00: por default value (zero scale) 01: zero scale (ground) 10: midscale 11: full scale (reference) aux mode (b[3:2]) the mode in which the aux input will operate: 00: pin disabled 01: enable ldac functionality 10: enable clr functionality. default after por. 11: pin disabled power-down mode (pd) (b[1:0]) power-down mode for the device: 00: normal operation: the dac will be powered up and returned to its previous setting. default after por. 01: power-down: the dac core will be powered down and v out is high-impedance. 10: power-down: the dac core will be powered down and v out is connected to ground via 100ki. 11: power-down: the dac core will be powered down and v out is connected to ground via 1ki. maxim integrated max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface
22 table 13. user readback command and content user read command descriptions the max5215/max5217 allow the user to read back the data for supported registers. table 13 lists the user readback commands and the 2 data byte contents being read back. for the max5215, code and dac read back, the data content is left justified and the 2 lsbs ([1:0]) of the input 2-byte data are not used and read out as 0. applications information power-on reset (por) when power is applied to v dd , the input registers are set to zero so the dac output is set to code zero. initially the device powers up to an untrimmed zero code setting. the device will operate in a fully trimmed mode following the first i 2 c operation which modifies dac latch content. power supplies and bypassing consideations bypass v dd with high-quality ceramic capacitors to a low-impedance ground as close as possible to the device. minimize lead lengths to reduce lead inductance. connect the gnd input to the analog ground plane. layout considerations digital and ac transient signals on gnd can create noise at the output. connect gnd to form the star ground for the dac system. refer remote dac loads to this system ground for the best possible performance. use proper grounding techniques, such as a multilayer board with a low-inductance ground plane, or star connect all ground return paths back to the max5215/max5217 gnd. carefully lay out the traces to reduce ac cross-coupling. do not use wire-wrapped boards and sockets. use shielding to improve noise immunity. do not run analog and digital signals parallel to one another, especially clock signals. avoid routing digital lines underneath the max5215/max5217 package. r7 r6 r5 r4 r3 r2 r1 r0 read command read data1 high byte d[15:8] read data1 low byte d[7:0] 0 0 0 0 0 0 0 0 id readback (0x00) 0011100, clear status (0x11) 0 0 0 0 0 0 0 1 code_load readback (0x01) dac_latch[15:8] dac_latch[7:0] 0 0 0 0 0 0 1 0 code readback (0x02) code_register[15:8] code_register[7:0] 0 0 0 0 0 0 1 1 load readback (0x03) dac_latch[15:8] dac_latch[7:0] 0 0 0 0 0 1 0 1 code_load_m readback (0x05) dac_latch[15:8] dac_latch[7:0] 0 0 0 0 0 1 1 0 code_m readback (0x06) code_register[15:8] code_register[7:0] 0 0 0 0 1 0 0 0 config readback (0x08) 0000_0000 00, clear_value[1:0], aux_mode[1:0], pd[1:0] maxim integrated max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface
23 definitions integral nonlinearity (inl) inl is the deviation of the measured transfer function from a straight line drawn between two codes once offset and gain errors have been nullified. differential nonlinearity (dnl) dnl is the difference between an actual step height and the ideal value of 1 lsb. if the magnitude of the dnl is greater than -1 lsb, the dac guarantees no missing codes and is monotonic. offset error offset error indicates how well the actual transfer function matches the ideal transfer function. the offset error is calculated from two measurements near zero code and near maximum code. gain error gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corresponds to the same percentage error in each step. settling time the settling time is the amount of time required from the start of a transition, until the dac output settles to the new output value within the measurments specified accuracy. digital feedthrough digital feedthrough is the amount of noise that appears on the dac output when the dac digital control lines are toggled. digital-to-analog glitch impulse a major carry transition occurs at the midscale point where the msb changes from low to high and all other bits change from high to low, or where the msb changes from high to low and all other bits change from low to high. the duration of the magnitude of the switching glitch during a major carry transition is referred to as the digital-to-analog glitch impulse. digital-to-analog power-up glitch impulse the digital-to-analog power-up glitch is the duration of the magnitude of the switching glitch that occurs as the device exits power-down mode. maxim integrated max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface
24 typical operating circuit dac c addr aux v ref_in v ref_out v out scl sda out gnd v dd v+ v+ ref 100nf unipolar operation 4.7f 100nf dac c addr aux v ref_in v ref_out v out r1 r1 = r2 v+ v+ v- v- scl sda out gnd v dd ref 100nf bipolar operation 4.7f 100nf max6133 max5215 max5217 max6133 max5215 max5217 r2 v out = -v ref to +v ref v out = 0v to v ref maxim integrated max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface
25 ordering information note: all devices are specified over the -40c to +105c operating temperature range. + denotes a lead(pb)Cfree/rohs-compliant package. *future productcontact factory for availability. chip information process: bicmos package information for the latest package outline information and land patterns (foot- prints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. part pin-package resolution (bits) inl max (lsb) max5215gua+ 8 fmax 14 q1 MAX5217GUA+ 8 fmax 16 q4 max5217bgua+ 8 fmax 16 q8 package type package code outline no. land pattern no. 8 fmax u8+3 21-0036 90-0092 maxim integrated max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 26 ? 2012 maxim integrated the maxim logo and maxim integrated are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 11/12 initial release max5215/max5217 14-/16-bit, low-power, buffered output, rail-to-rail dacs with i 2 c interface
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